Semiconductor device and method of fabricating the same

ABSTRACT

According to example embodiments, a semiconductor device may include a substrate having an upper surface defining a groove and an active region, a device isolation layer in the groove, and a contact structure on the active region. The device isolation exposes the active region and may have a top surface that is higher than a top surface of the active region. The contact structure may include a first portion filling a gap region delimited by a sidewall of the device isolation layer and the top surface of the active region, the contact structure may include and a second portion on the device isolation layer so the second portion overlaps with the device isolation layer in a plan view.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2012-0095799, filed onAug. 30, 2012, in the Korean Intellectual Property Office, the entirecontents of which are hereby incorporated by reference.

BACKGROUND

Example embodiments of inventive concepts relate to a semiconductordevice and/or a method of fabricating the same.

Due to their small-sized, multifunctional, and/or low-costcharacteristics, semiconductor devices are being esteemed as importantelements in the electronic industry. Higher integration of semiconductordevices, such as semiconductor memory devices, is desired to satisfyconsumer demands for superior performance and inexpensive prices. In thecase of semiconductor memory devices, increased integration isespecially desired, because their integration is an important factor indetermining product prices. However, expensive process equipment forincreasing pattern fineness sets a practical limitation on increasingintegration for semiconductor memory devices. Thus, a variety of studieshave been recently done on new technology for increasing integrationdensity of a semiconductor device.

SUMMARY

Example embodiments of inventive concepts relate to a semiconductordevice with improved electric characteristics.

According to example embodiments of inventive concepts, a semiconductordevice may include: a substrate having an upper surface, the uppersurface of the substrate defining a groove and an active region; adevice isolation layer in the groove of the substrate, the deviceisolation layer exposing the active region and having a top surface thatis higher than a top surface of the active region of the substrate; anda contact structure on the active region. The contact structure mayinclude a first portion filling a gap region delimited by a sidewall ofthe device isolation layer and a top surface of the active region, and asecond portion on the device isolation layer so the second portionoverlaps with the device isolation layer in a plan view.

In example embodiments, the first portion may contact the sidewall ofthe device isolation layer, and the first portion may contact the topsurface of the active region.

In example embodiments, the active region may include a first activeregion in a cell array region of the substrate. The first active regionmay include a first impurity region and a second impurity region, and abottom surface of the first portion may cover an entire area of a topsurface of the second impurity region in the first active region.

In example embodiments, the device may further include conductive lineson the substrate. The second portion may be between the conductivelines, and the first portion may extend below the conductive lines.

In example embodiments, the device may further include a cell gatestructure buried in the substrate. A portion of the gap region may bedelimited by a sidewall of the cell gate structure.

In example embodiments, a sidewall of the first portion may be incontact with the sidewall of the cell gate structure.

In example embodiments, the active region may include a first impurityregion and a second impurity region, the first impurity region and thesecond impurity region may be at both sides of the cell gate structure,and the contact structure may be connected to the second impurityregion.

In example embodiments, the device may further include a data storingelement connected to the contact structure.

In example embodiments, the data storing element may include a lowerelectrode, an upper electrode and an insulating layer, and theinsulating layer may be between the lower and upper electrodes.

In example embodiments, the device may further include conductive lineson the substrate. The conductive lines may cross the cell gatestructure. The first impurity region may be connected to the conductivelines.

In example embodiments, the conductive lines may include a third portionand a fourth portion. The third portion may overlap with the deviceisolation layer in a plan view. The fourth portion may extend from thethird portion toward the substrate and fill a region delimited by thesidewall of the device isolation layer and a top surface of the firstimpurity region.

In example embodiments, the device may further include a firstinterlayered insulating pattern between the conductive lines; and anetch stop layer. The first interlayered insulating pattern may delimitthe second portion along with the conductive lines. The etch stop layermay be between the device isolation layer and the conductive lines, andthe etch stop layer may include a material having an etch selectivitywith respect to the first interlayered insulating pattern.

In example embodiments, the top surface of the device isolation layermay define a trench. The cell gate structure may include a gateinsulating layer in the trench, a gate conductive layer in the trenchand on the gate insulating layer, and a capping layer on top surfaces ofthe gate insulating layer and the gate conductive layer. The cappinglayer may fill the trench.

In example embodiments, the device may further include a peripheral gatestructure, the substrate may include a cell region and a peripheralcircuit region, the cell gate structure may be on the cell region of thesubstrate, and the peripheral gate structure may be on the peripheralcircuit region of the substrate. The upper surface of the substrate onthe peripheral circuit region may be lower than an upper surface of thecapping layer.

In example embodiments, the contact structure may further include aconductive etch stop layer between the first portion and the activeregion, and the conductive etch stop layer may extend along the sidewallof the device isolation layer.

According to example embodiments of inventive concepts, a semiconductordevice may include a device isolation on the substrate; conductivelines; and a contract structure. The device isolation layer may exposean active region of the substrate. The contact structure may be betweenthe conductive lines and connected to the active region. The contactstructure may include a lower portion that extends below the conductivelines.

In example embodiments, the lower portion of the contact structure mayfill a gap region delimited by a sidewall of the device isolation layerand a top surface of the active region.

In example embodiments, the contact structure may include an upperportion, and the upper portion may overlap with the device isolationlayer in a plan view.

In example embodiments, the device may further include a cell gatestructure buried in the substrate. A portion of the gap region may bedelimited by a sidewall of the cell gate structure.

In example embodiments, the device may further include a first impurityregion and a second impurity region. The first impurity region and thesecond impurity region may be at both sides of the cell gate structure.The contact structure may be connected to the second impurity region andeach of the conductive lines may be connected to the first impurityregion.

According to example embodiments of inventive concept, a method offabricating a semiconductor device may include: forming a sacrificialpattern on an active region of a substrate; forming conductive lines onthe sacrificial pattern, the conductive lines crossing the activeregion; forming a preliminary contact hole between the conductive lines,the preliminary contact hole exposing the sacrificial pattern;selectively removing the sacrificial pattern to extend the preliminarycontact hole toward the substrate, thereby forming a contact hole; andforming a contact structure in the contact hole.

In example embodiments, the forming of the sacrificial pattern mayinclude: forming a sacrificial layer on the substrate; patterning thesacrificial layer to form a preliminary sacrificial pattern on thesubstrate; and forming a device isolation layer in areas of thesubstrate that are exposed by the preliminary sacrificial pattern. Thedevice isolation layer may expose the active region.

In example embodiments, a material of the sacrificial layer may have anetch selectivity with respect to the device isolation layer and thesubstrate.

In example embodiments, the sacrificial layer may include at least oneof a silicon-germanium compound, silicon nitride, silicon oxynitride, ora silicon-metal compound.

In example embodiments, an upper surface of the substrate may include acell array region and a peripheral circuit region, and forming thesacrificial layer on the substrate may include forming the sacrificiallayer on the cell array region and the peripheral circuit region of thesubstrate.

In example embodiments, the method may further include removing aportion of the sacrificial layer on the peripheral circuit region; andsequentially forming a peripheral gate insulating layer and a peripheralgate electrode on the peripheral circuit region after the portion of thesacrificial layer on the peripheral circuit region is removed.

In example embodiments, the forming the preliminary contact hole mayinclude exposing a top surface of the device isolation layer.

In example embodiments, the conductive lines may overlap the sacrificialpattern in a plan view, and the forming the contact structure in thecontact hole may include forming a portion of the contact structure thatextends below the conductive lines.

In example embodiments, the method may further include: forming animpurity region in an upper portion of the substrate, the impurityregion including a first impurity region and a second impurity region;and forming a cell gate structure buried in the substrate. The firstimpurity region and the second impurity region may be separated by thecell gate structure, and the sacrificial pattern may include a firstsacrificial pattern and a second sacrificial pattern separated by thecell gate structure.

In example embodiments, the forming the preliminary contact hole mayinclude exposing the second sacrificial pattern, the forming the contacthole may include exposing the second impurity region.

In example embodiments, the forming the impurity region may includeforming a plurality of impurity region, the forming the contact hole mayinclude forming a plurality of contact holes, and the forming thepreliminary contact hole may include forming a plurality of preliminarycontact holes. Each of the plurality of the preliminary contact holesmay be formed to have two or more different depths.

In example embodiments, each of the plurality of the contact holes maybe formed to have a substantially same depth.

In example embodiments, the forming the conductive lines may includeremoving the first sacrificial pattern to expose the first impurityregion.

In example embodiments, the forming the conductive lines may furtherinclude forming a semiconductor layer to cover the first and secondsacrificial patterns, and the removing the first sacrificial pattern mayinclude forming a through hole to penetrate the semiconductor layer andexpose the first impurity region.

In example embodiments, the forming the through hole may include etchingthe semiconductor layer to expose the first sacrificial pattern, andselectively removing the first sacrificial pattern.

In example embodiments, the forming of the sacrificial pattern mayinclude: forming a device isolation layer on the substrate, the deviceisolation layer exposing an active layer of the substrate; forming arecess region in the substrate by etching an upper portion of theexposed upper surface in a cell array region of the substrate; formingthe sacrificial pattern in the recess region.

In example embodiments, the method may further include forming a firstetch stop layer in the recess region, before the forming the sacrificialpattern in the recess region.

In example embodiments, the first etch stop layer may include aconductive material.

In example embodiments, the method may further include forming an etchstop layer between the sacrificial pattern and the conductive lines.

In example embodiments, the forming the preliminary contact hole mayinclude an etching process that exposes an upper surface of the etchstop layer.

According to example embodiments of inventive concepts, a semiconductordevice may include: a substrate having an upper surface; and a pluralityof contact structures that are spaced apart from each other. The uppersurface of the substrate may define first active region that protrudefrom the substrate and are separated by a groove, each one of the firstactive regions may include a first impurity region between a pair ofsecond impurity regions. The plurality of contact structure may eachinclude a first portion on a corresponding one of the second impurityregions and a second portion that extends vertically from a part of anupper surface of the first portion. Each second portion may include alower surface that partially overlaps the groove in a plan view.

In example embodiments, the device may further include a deviceisolation layer in the groove. The device isolation layer may expose thefirst active regions, and the device isolation layer may include a topsurface that is higher than a top surface of the first active regions.

In example embodiments, the device may further include a plurality ofbit lines that are spaced apart from each other on the substrate. Thebit lines may extend in a first direction. Each one of the bit lines maybe electrically connected to the first impurity region and electricallyisolated from the second impurity regions of at least two adjacent firstactive regions.

In example embodiments, the device may further include a plurality ofword line structures embedded in the device isolation layer, wherein theplurality of word line structures may extend in a second directioncrossing the first direction.

In example embodiments, the device may further include a peripheral gatestructure. The substrate may include a cell array region and aperipheral circuit region. The first active regions may be in the cellarray region of the substrate. The upper surface of the substrate mayfurther define a second active region in the peripheral circuit regionof the substrate. The second active region may be spaced apart from thefirst active regions. The peripheral gate structure may be on the secondactive region.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingbrief description taken in conjunction with the accompanying drawings.The accompanying drawings represent non-limiting example embodiments asdescribed herein. In the drawings:

FIGS. 1A through 11A are plan views illustrating semiconductor devicesand methods of fabricating the same, according to example embodiments ofinventive concepts.

FIGS. 1B through 11B are sectional views taken along line A-A′ of FIGS.1A through 11A, respectively.

FIGS. 1C through 11C are sectional views taken along lines B-B′ and C-C′of FIGS. 1A through 11A, respectively.

FIG. 1D is an enlarged plan view of a region Q of FIG. 1A.

FIGS. 12A through 14A are sectional views taken along the line A-A′ ofFIG. 1A and illustrate semiconductor devices and methods of fabricatingthe same according to example embodiments of inventive concepts.

FIGS. 12B through 14B are sectional views taken along the lines B-B′ andC-C′ of FIG. 1A.

FIGS. 15A through 23A are plan views illustrating methods of fabricatinga semiconductor device according to example embodiments of inventiveconcepts.

FIGS. 15B through 23B are sectional views taken along line A-A′ of FIGS.15A through 23A, respectively.

FIGS. 15C through 23C are sectional views taken along lines B-B′ andC-C′ of FIGS. 15A through 23A, respectively.

FIGS. 24A and 24B are sectional views illustrating semiconductor devicesaccording to example embodiments of inventive concepts.

FIGS. 25A through 29A are plan views illustrating methods of fabricatinga semiconductor device according to example embodiments of inventiveconcepts.

FIGS. 25B through 29B are sectional views taken along line A-A′ of FIGS.25A through 29A, respectively.

FIGS. 25C through 29C are sectional views taken along lines B-B′ andC-C′ of FIGS. 25A through 29A, respectively.

FIG. 30 is a block diagram schematically illustrating electronic devicesincluding a semiconductor device according to example embodiments ofinventive concepts.

FIG. 31 is a block diagram schematically illustrating memory systemsincluding a semiconductor device according to example embodiments ofinventive concepts.

It should be noted that these figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feature.

DETAILED DESCRIPTION

Example embodiments of inventive concept will now be described morefully with reference to the accompanying drawings, in which exampleembodiments are shown. Example embodiments of inventive concept may,however, be embodied in many different forms and should not be construedas being limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the concept of example embodiments tothose of ordinary skill in the art. In the drawings, the thicknesses oflayers and regions are exaggerated for clarity. Like reference numeralsin the drawings denote like elements, and thus their description will beomitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers indicate like elementsthroughout. As used herein the term “and/or” includes any and allcombinations of one or more of the associated listed items. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon”).

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof. Expressions such as “atleast one of,” when preceding a list of elements, modify the entire listof elements and do not modify the individual elements of the list.

Example embodiments of inventive concept are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofexample embodiments. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, example embodiments ofinventive concept should not be construed as limited to the particularshapes of regions illustrated herein but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may have rounded or curvedfeatures and/or a gradient of implant concentration at its edges ratherthan a binary change from implanted to non-implanted region. Likewise, aburied region formed by implantation may result in some implantation inthe region between the buried region and the surface through which theimplantation takes place. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to illustratethe actual shape of a region of a device and are not intended to limitthe scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments of inventiveconcept belong. It will be further understood that terms, such as thosedefined in commonly-used dictionaries, should be interpreted as having ameaning that is consistent with their meaning in the context of therelevant art and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

A dynamic random access memory (DRAM) will be described as an example ofa semiconductor device according to example embodiments of inventiveconcepts, but example embodiments of inventive concepts are limitedthereto. For example, example embodiments of inventive concepts mayinclude a magnetic memory device (MRAM), a phase-changeable memorydevice (PRAM), ferroelectric memory device (FRAM), a resistive memorydevice (RRAM), and so forth.

FIG. 1A is a plan view illustrating a semiconductor device according toexample embodiments of inventive concepts. FIG. 1B is a sectional viewtaken along line A-A′ of FIG. 1A, and FIG. 1C is a sectional view takenalong lines B-B′ and C-C′ of FIG. 1A. FIG. 1D is an enlarged plan viewof a region Q of FIG. 1A.

Referring to FIGS. 1A through 1D, a substrate 100 may be provided toinclude a cell array region CAR and a peripheral circuit region PCR. Thesubstrate 100 may be, for example, a semiconductor substrate (e.g., ofsilicon, germanium, silicon-germanium). In example embodiments, memorycells may be provided on the cell array region CAR. A word line driver,a sense amplifier, row and column decoders, and control circuits may beprovided on the peripheral circuit region PCR. An upper surface of thesubstrate 100 may define first active regions ACT1 in the cell arrayregion CAR and second active region ACT2 in the peripheral circuitregion PCR, and a groove G. A device isolation layer 101 may be formedin the groove G. The device isolation layer 101 may have a top surfacethat is higher than top surfaces of the active regions ACT1 and ACT2adjacent thereto. The first active regions ACT1 may be horizontallyseparated from each other to have a bar-shaped structure and extendalong a third direction (hereinafter, s direction) at an angle to afirst direction (hereinafter, x direction) and a second direction(hereinafter, y direction). In example embodiments, the first activeregions ACT1 may be spaced apart from each other with two or morey-directional distances.

First and second impurity regions 21 and 22 may be provided on the firstactive regions ACT1. The impurity regions 21 and 22 may be regions dopedwith impurities having a different conductivity type from the substrate100. In each first active region ACT1, the first impurity region 21 maybe provided between a pair of the second impurity regions 22, and thefirst impurity region 21 and the second impurity regions 22 may beseparated from each other by trenches 11 and/or the groove G in thesubstrate 100.

Cell gate structures may be provided in the cell array region CAR to beburied in the substrate 100. In other words, the cell gate structuresmay include word line structures WS of the semiconductor device, and theword line structures WS may be provided in the trenches 11 and extendalong the y direction. Each of the word line structures WS may include agate insulating layer 121, a gate electrode 126 and a gate cappingpattern 129, which are sequentially stacked in a corresponding one ofthe trenches 11.

Conductive lines may be provided on the cell array region CAR. Inexample embodiments, the conductive lines may be connected to the firstimpurity regions 21 and extend along the x direction. The conductivelines may serve as bit line structures BS. A peripheral gate structurePG may be provided on the peripheral circuit region PCR. Each of the bitline structures BS and the peripheral gate structure PG may include afirst conductive pattern, a second conductive pattern, and a barrierpattern between the first and second conductive patterns. For example,each of the bit line structures BS may include a first conductivepattern 147 connected to the first impurity region 21, and a barrierpattern 152, a second conductive pattern 162, and a capping pattern 172that are sequentially stacked on the first conductive pattern 147. Thebit line structures BS may include separation patterns between the firstconductive patterns 147. For example, the separation patterns may befirst semiconductor patterns 141. The first semiconductor patterns 141may include an undoped poly silicon layer. The barrier pattern 152 onthe cell array region CAR may extend along the x direction and have abottom surface that is alternatingly in contact with the firstconductive patterns 147 and the first semiconductor patterns 141.

Although FIG. 1B illustrates a bottom surface of the first conductivepattern 147 is at about the same height as a top surface of the secondimpurity region, example embodiments of inventive concepts are notlimited thereto. For example, a bottom surface of the first conductivepattern 147 may be lower than top surfaces of the second impurityregions 22. Although the separation patterns may be first semiconductorpatterns 141, example embodiments are not limited thereto. For example,in example embodiments of inventive concepts, the separation patternsmay alternatively be an insulating pattern such as a silicon oxide layeror a silicon oxynitride layer instead of the first semiconductorpatterns 141.

The structural features of semiconductor device according to exampleembodiments of inventive concepts will be explained in more detail withreference to a fabricating method according to example embodiments ofinventive concepts to be described below.

The peripheral gate structure PG may include a gate insulating layer132, a first conductive pattern 143, a barrier pattern 153, a secondconductive pattern 163 and a capping pattern 173 sequentially formed onthe substrate 100. The bit line structures BS and the peripheral gatestructure PG may further include a first spacer SP1 and a second spacerSP2, respectively.

The first conductive patterns 147 on the cell array region CAR and thefirst conductive pattern 143 on the peripheral circuit region PCR mayinclude a same material. For example, the first conductive patterns 147and 143 may be formed of a doped polysilicon layer. The first conductivepatterns 147 on the cell array region CAR may have a conductivity typethat is identical to or different than a conductivity type of the firstconductive pattern 143 on the peripheral circuit region PCR.

The second conductive pattern 162 on the cell array region CAR may beformed to include the same material as the second conductive pattern 163on the peripheral circuit region PCR. For example, the second conductivepatterns 162 and 163 may include at least one of W, Ti, or Ta. Thecapping patterns 172 and 173 and the spacers SP1 and SP2 may include adielectric material such as at least one of silicon oxide, siliconnitride or silicon oxynitride.

The barrier pattern 152 on the cell array region CAR may be formed toinclude a same material as the barrier pattern 153 on the peripheralcircuit region PCR. In example embodiments, the barrier patterns 152 and153 may include at least one of metal-silicon compounds and/orconductive metal nitrides. For example, the barrier patterns 152 and 153may include at least one of WN and/or WSi.

Data storing elements may be provided to be connected to the secondimpurity regions 22. In the case that the semiconductor device is adynamic random access memory (DRAM) device, capacitors CAP electricallyconnected to the second impurity regions 22 may be provided as the datastoring elements. The capacitors CAP may include lower electrodes 182,an upper electrode 184, and a dielectric layer 183 interposed betweenthe lower electrodes and the upper electrode 184.

The capacitors CAP may be connected to the second impurity regions 22through contact structures CT. The contact structures CT may be providedin contact holes ECH that are formed between the bit line structures BS.Each of the contact structures CT may include a first portion CP1filling a gap region GP that is delimited by a sidewall of the deviceisolation layer 101 and a top surface of the first active region ACT1(or a top surface of the second impurity regions 22). As shown in FIG.1D, the gap region GP may be delimited by a sidewall SD of the word linestructure WS. In other words, the gap region GP may be defined by thesidewall of the device isolation layer 101 and the sidewall SD of theword line structure WS. The contact structures CT may further include asecond portion CP2 extending from the first portion CP1 and beingoverlapped with the device isolation layer 101, when viewed from a planview.

The first portion CP1 may be in contact with the sidewall of the deviceisolation layer 101 and the top surface of the second impurity regions22. The first portion CP1 may be in contact with the sidewall SD of theword line structure WS. The bottom surface of the first portion CP1 maybe formed to cover fully the top surfaces of cover the second impurityregions 22. For example, as shown in FIG. 1D, the bottom surface of thefirst portion CP1 may have substantially the same area as that of thetop surface of the second impurity region 22. The first portion CP1 maybe overlapped with the bit line structures BS, in plan view, and thefirst portion CP1 may extend below the bit line structures BS.

The second portion CP2 may extend between the bit line structures BS.For example, the second portion CP2 may be in contact with the sidewallof the bit line structures BS and a sidewall of a first interlayeredinsulating pattern 82. The first interlayered insulating patterns 82 mayinclude at least one of a silicon oxide layer, a silicon oxynitridelayer, or a silicon nitride layer. The contact structures CT may includeat least one of a doped polysilicon layer, metals, conductive metalnitride layers, or metal-semiconductor compounds.

Contact pads 115 may be provided between the contact structures CT andthe capacitors CAP. The contact pads 115 may be provided in a secondinterlayered insulating layer 116 and connect the contact structures CTelectrically to the lower electrodes 182. The second interlayeredinsulating layer 116 may include at least one of a silicon oxide layer,a silicon oxynitride layer, or a silicon nitride layer.

A peripheral contact 186 may be provided through a first interlayeredinsulating layer 81 and the second interlayered insulating layer 116 andbe connected to a third impurity region 23 of the peripheral circuitregion PCR. The peripheral contact 186 may be connected to a peripheralconductive line 185. A third interlayered insulating layer 117 may beprovided on the peripheral conductive line 185. The peripheralconductive line 185 may be electrically connected to the bit linestructures BS, but example embodiments of inventive concept may not belimited thereto.

According to example embodiments of inventive concepts, the contactstructures CT may be in contact with the second impurity regions 22 in auniform contact area. In addition, the contact structures CT may beprovided to have a uniform depth to the top surface of the secondimpurity regions 22. Accordingly, it is possible to limit (and/orprevent) an increase in leakage current or contact resistance that mayoccur when the contact holes ECH are misaligned to the second impurityregion 22.

FIGS. 2A through 11A are plan views illustrating a method of fabricatinga semiconductor device according to example embodiments of inventiveconcepts. FIGS. 2B through 11B are sectional views taken along line A-A′of FIGS. 2A through 11A, respectively. FIGS. 2C through 11C aresectional views taken along lines B-B′ and C-C′ of FIGS. 2A through 11A,respectively.

Referring to FIGS. 2A, 2B and 2C, impurity region 20 may be formed inthe cell array region CAR of the substrate 100. The substrate 100 maybe, for example, a semiconductor substrate (e.g., of silicon, germanium,silicon-germanium). The impurity region 20 may be formed by an ionimplantation process injecting impurities ions with a differentconductivity type from the substrate 100 into an upper portion of thesubstrate 100. In other embodiments, the impurity region 20 may beformed in a subsequent process. A mask pattern (not shown) may be formedon the peripheral circuit region PCR, and this limits (and/or prevents)the impurity region 20 from being formed in the peripheral circuitregion PCR. The mask pattern may be removed after the ion implantationprocess.

A sacrificial layer 70 may be formed on the substrate 100. Thesacrificial layer 70 may be formed on the cell array region CAR and theperipheral circuit region PCR. The sacrificial layer 70 may be formed ofa material having an etch selectivity with respect to the substrate 100and a device isolation layer to be described below. In other words, thesacrificial layer 70 may be formed of a material that may be etched at adifferent (e.g., slower) rate than an etch rate of the substrate 100using a desired etchant. For example, the sacrificial layer 70 may beformed of at least one of silicon-germanium compounds, a silicon nitridelayer, a silicon oxynitride layer, or silicon-metal compounds.

Referring to FIGS. 3A, 3B and 3C, the device isolation layers 101 may beformed on the substrate 100 to delimit the first active regions ACT1 inthe cell array region CAR and the second active region ACT2 in theperipheral circuit region PCR. The first active regions ACT1 may behorizontally separated from each other to have a bar-shaped structureand extend along a third direction (hereinafter, s direction) at anangle to both of the first direction (hereinafter, x direction) and thesecond direction (hereinafter, y direction). Here, the x direction andthe y direction may be directions crossing each other. The sacrificiallayer 70 may be patterned along with the upper portion of the substrate100, thereby forming preliminary sacrificial patterns 74 provided on thefirst active regions ACT1 and the second active region ACT2,respectively.

Referring to FIGS. 4A, 4B and 4C, the trenches 11 may be formed in thecell array region CAR of the substrate 100. The trenches 11 may extendalong the y direction and be spaced apart from each other in the xdirection, such that the impurity region 20 may be separated into thefirst impurity regions 21 and the second impurity regions 22. In otherwords, in each of the first active region ACT1, the first impurityregion 21 may be provided between a pair of the second impurity regions22, and the first impurity region 21 and the second impurity regions 22may be separated from each other by the trenches 11. The trenches 11 mayseparate the preliminary sacrificial pattern 74 into a plurality ofsacrificial patterns. Hereinafter, sacrificial patterns on the firstimpurity regions 21 will be referred to as “first sacrificial patterns71” and sacrificial patterns on the second impurity regions 22 will bereferred to as “second sacrificial patterns 72”. Sacrificial patterns onthe peripheral circuit region PCR will be referred to as “thirdsacrificial pattern 73”.

The trenches 11 may be formed by forming a mask pattern 111 on thesubstrate 100 and performing a dry and/or wet etching process using themask pattern 111 as an etch mask. In example embodiments, the maskpattern 111 may include at least one of a photo resist layer, a siliconnitride layer, or a silicon oxide layer. A depth of the trench 11 may beless than that of the device isolation layer 101.

A first insulating layer 120, a conductive layer 125, and a fillinglayer 128 may be sequentially formed on the resulting structure providedwith the trenches 11. The first insulating layer 120 and the conductivelayer 125 may be formed in the trenches 11, and then, the filling layer128 may be formed to fill the trenches 11 provided with the firstinsulating layer 120 and the conductive layer 125. The formation of thefilling layer 128 may include forming an insulating layer on theconductive layer 125 and then performing a planarization process.

In example embodiments, the first insulating layer 120 may include atleast one of a silicon oxide layer, a silicon nitride layer, or asilicon oxynitride layer. The conductive layer 125 may include at leastone of doped semiconductor materials, conductive metal nitrides, metals,or metal-semiconductor compounds. The filling layer 128 may include atleast one of a silicon oxide layer, a silicon nitride layer, or asilicon oxynitride layer. Each of the first insulating layer 120, theconductive layer 125, and the filling layer 128 may be formed using atleast one of a chemical vapor deposition (CVD), a physical vapordeposition (PVD), or an atomic layer deposition (ALD).

Referring to FIGS. 5A, 5B, and 5C, the first insulating layer 120 andthe conductive layer 125 may be etched and localized into the trenches11. As the result of the etching process, the first insulating layer 120may form the gate insulating layers 121 separated from each other andthe conductive layer 125 may form the gate electrodes 126 separated fromeach other. The etching process may be performed until the filling layer128 is removed, and thus, the gate insulating layers 121 and the gateelectrodes 126 may have top surfaces that are lower than top surfaces ofthe trenches 11. The mask pattern 111 may be removed during the etchingprocess. The first insulating layer 120 and the conductive layer 125provided on the peripheral circuit region PCR may be removed during theetching process.

The gate capping patterns 129 may be formed on the gate electrodes 126.The gate capping patterns 129 may be formed by forming an insulatinglayer to fill remaining portions of the trenches 11 provided with thegate electrodes 126 and performing a planarization process to expose thetop surface of the substrate 100. The insulating layer provided on theperipheral circuit region PCR may be removed by the planarizationprocess. The gate capping patterns 129 may include at least one of asilicon nitride layer, a silicon oxide layer, or a silicon oxynitridelayer. As the result of the formation of the gate capping patterns 129,cell gate structures may be formed in the trenches 11. The cell gatestructures may serve as word line structures WS of the semiconductordevice.

Referring to FIGS. 6A, 6B, and 6C, the third sacrificial pattern 73 maybe removed from the peripheral circuit region PCR. As the result of theremoval of the third sacrificial pattern 73, the exposed top surface ofthe substrate 100 of the peripheral circuit region PCR may be lower thanthe top surface of the gate capping patterns 129 of the cell arrayregion CAR. The removal of the third sacrificial pattern 73 may includeforming a mask pattern 112 to cover the cell array region CAR and thenselectively etching the third sacrificial pattern 73 exposed by the maskpattern 112. In example embodiments, the mask pattern 112 may include atleast one of a photo resist layer, a silicon nitride layer, or a siliconoxide layer. The selective etching process of the third sacrificialpattern 73 may be performed using an etching solution or an etching gas,which is selected to suppress the substrate 100 and the device isolationlayer 101 from being etched and to selectively remove the thirdsacrificial pattern 73. For example, in the case where the thirdsacrificial pattern 73 includes silicon-germanium, the selective removalof the third sacrificial pattern 73 may be performed using an etchingsolution containing peracetic acid. The etching solution may furthercontain hydrofluoric acid (HF) solution and deionized water. In exampleembodiments, in the case where the third sacrificial pattern 73 includesa silicon nitride layer, the selective removal of the third sacrificialpattern 73 may be performed using an etching solution containingphosphoric acid (H₃PO₄).

After the removal of the third sacrificial pattern 73, a secondinsulating layer 131 may be formed on the peripheral circuit region PCR.The second insulating layer 131 may include at least one of siliconoxide, silicon oxynitride, or high-k dielectrics having a higherdielectric constant than silicon oxide. In example embodiments, thesecond insulating layer 131 may be formed using a thermal oxidationprocess.

Referring to FIGS. 7A, 7B, and 7C, after the removal of the mask pattern112, the first semiconductor patterns 141 may be formed on the cellarray region CAR and the peripheral circuit region PCR. For example, thefirst semiconductor patterns 141 may be formed of an un-doped siliconlayer. Through holes 12 may be formed to expose the first impurityregions 21 through the first semiconductor patterns 141. The firstsacrificial patterns 71 may be removed by the formation of the throughholes 12. In example embodiments, the through holes 12 may be formed tohave a section shaped like a circle or an ellipse, in plan view. Theformation of the through holes 12 may include forming a mask pattern 113on the first semiconductor patterns 141, and then, performing a dryand/or wet etching process using the mask pattern 113 as an etch mask.The first semiconductor patterns 141 on the peripheral circuit regionPCR may be doped with impurities ions, before or after the formation ofthe through holes 12. In example embodiments, a mask pattern (not shown)may be formed to cover the cell array region CAR, and an ionimplantation process may be performed to the first semiconductorpatterns 141 on the peripheral circuit region PCR. The firstsemiconductor patterns 141 doped with impurities may have a conductivitytype of p- or n-type, depending on whether the transistor on theperipheral circuit region PCR is a PMOS transistor or an NMOStransistor.

Referring to FIGS. 8A, 8B, and 8C, the first conductive patterns 147 maybe formed to fill the through holes 12. In example embodiments, thefirst conductive patterns 147 may be a doped silicon layer. The firstconductive patterns 147 may be formed by removing the mask pattern 113,forming a semiconductor layer to fill the through holes 12, and then,performing a planarization process. The first conductive patterns 147may be doped in an in-situ manner and have the same conductivity type asthe first impurity regions 21.

A barrier layer, a second conductive layer and a capping layer may besequentially formed on the resulting structure provided with the firstconductive patterns 147. The first semiconductor patterns 141, thebarrier layer, the second conductive layer and the capping layer may bepatterned to form conductive lines on the cell array region CAR and aperipheral gate structure PG on the peripheral circuit region PCR. Theconductive lines may serve as bit line structures BS of thesemiconductor device. The bit line structures BS may include a pluralityof first conductive patterns 147 coupled to the first impurity regions21, respectively, and the barrier pattern 152, the second conductivepattern 162, and the capping pattern 172 sequentially stacked on thefirst conductive patterns 147. The peripheral gate structure PG mayinclude the gate insulating layer 132, the first conductive pattern 143,the barrier pattern 153, the second conductive pattern 163 and thecapping pattern 173 that are sequentially stacked on the substrate 100.The formation of the bit line structures BS and the peripheral gatestructure PG may include forming first spacers SP1 and second spacersSP2 on sidewalls of the bit line structures BS and the peripheral gatestructure PG, respectively.

In example embodiments, the barrier patterns 152 and 153 may beconfigured to limit (and/or prevent) metal atoms in the secondconductive patterns 162 and 163 from being diffused into the firstconductive patterns 147 and 143 or to realize an ohmic contact propertybetween the first conductive patterns 147 and 143 and the secondconductive patterns 162 and 163. For example, the barrier patterns 152and 153 may include at least one of conductive metal nitrides and/ormetal-silicon compounds. The barrier patterns 152 and 153 may be formedusing a CVD or ALD process.

The second conductive patterns 162 and 163 may include at least one ofmetals, conductive metal nitrides, or metal-silicon compounds. Forexample, the second conductive patterns 162 and 163 may include at leastone of W, Ti, or Ta. The capping patterns 172 and 173 may include atleast one of silicon oxide, silicon nitride or silicon oxynitride. Thesecond conductive patterns 162 and 163 and the capping patterns 172 and173 may be formed by a sputtering or CVD method.

The third impurity region 23 may be formed in the substrate 100 of theperipheral circuit region PCR to be adjacent to the peripheral gatestructure PG. The formation of the third impurity region 23 may includean ion implantation process to be performed on the substrate 100 exposedby the peripheral gate structure PG, and the ion implantation processmay be performed using impurities having the same conductivity type asthe first conductive pattern 143. During the formation of the thirdimpurity region 23, the cell array region CAR may be protected by a maskpattern provided thereon, but impurities provided to form the thirdimpurity region 23 may also be injected into the second impurity region22.

The first interlayered insulating layer 81 may be formed on theresulting structure provided with the bit line structures BS and theperipheral gate electrode PG. The first interlayered insulating layer 81may be formed to fill empty spaces between the bit line structures BS.For example, the first interlayered insulating layer 81 may include asilicon oxide layer and/or a silicon oxynitride. As the result of theplanarization process, the first interlayered insulating layer 81 may beformed to expose top surfaces of the capping patterns 172 and 173. Amask pattern 61 may be formed on the first interlayered insulating layer81. In the cell array region CAR, the mask pattern 61 may be formed tocross the bit line structures BS. In example embodiments, the maskpattern 61 may be formed to have a line shape extending parallel to theword line structures WS. The peripheral circuit region PCR may becovered with the mask pattern 61.

Referring to FIGS. 9A, 9B, and 9C, the first interlayered insulatinglayer 81 exposed by the mask pattern 61 may be etched to formpreliminary contact holes CH. The etching process may be performed usinga dry and/or wet etching process. During the etching process, the bitline structures BS exposed by the mask pattern 61 may be protected bythe capping pattern 172 and the first spacer SP1. As the result of theetching process, the first interlayered insulating layer 81 on the cellarray region CAR may be separated into the first interlayered insulatingpatterns 82 spaced apart from each other. Alternatively, the firstinterlayered insulating layer 81 on the peripheral circuit region PCRmay be protected by the mask pattern 61. The preliminary contact holesCH may be delimited by sidewalls of the bit line structures BS andsidewalls of the first interlayered insulating patterns 82. In exampleembodiments, upper portions of the second sacrificial patterns 72, thedevice isolation layer 101, and the gate capping patterns 129 may alsobe etched during the formation of the preliminary contact holes CH.

At least some of the preliminary contact holes CH may be formed to havea different depth from others of the preliminary contact holes CH. Forexample, a distance from the top surfaces of the gate capping patterns129 to the top surfaces of the second sacrificial patterns 72 exposed bythe preliminary contact holes CH may have several different values(e.g., d1, d2, and d3, where d2>d3>d1), as shown in FIG. 9C. Areas ofthe top surfaces of the second sacrificial patterns 72 exposed by thepreliminary contact holes CH may be different from each other. Thevariation in shape or structure of the preliminary contact holes CH mayresult from a difference in potion and relative configuration of thepreliminary contact holes CH and neighboring layers and structures(e.g., the bit line structures BS or the word line structures WS).

Referring to FIGS. 10A, 10B, and 10C, the second sacrificial patterns 72exposed by the preliminary contact holes CH may be removed to form thegap regions GP exposing the second impurity regions 22. The gap regionsGP may be delimited by the sidewall of the device isolation layer 101and the top surfaces of the second impurity regions 22. As the result ofthe formation of the gap regions GP, the preliminary contact holes CHmay extend toward the substrate 100 and form the contact holes ECH. Theremoval of the second sacrificial patterns 72 may include a selectiveetching process. For example, the selective etching process of thesecond sacrificial patterns 72 may be performed using an etchingsolution or an etching gas capable of suppressing the substrate 100 andthe device isolation layer 101 from being etched and of selectivelyremoving the second sacrificial patterns 72. For example, in the casewhere the second sacrificial patterns 72 include silicon-germanium, theselective removal of the second sacrificial patterns 72 may be performedusing an etching solution containing peracetic acid. The etchingsolution may further contain hydrofluoric acid (HF) solution anddeionized water. In example embodiments, in the case where the secondsacrificial patterns 72 include a silicon nitride layer, the selectiveremoval of the second sacrificial patterns 72 may be performed using anetching solution containing phosphoric acid (H₃PO₄). In spite of thedifference in depth between the preliminary contact holes CH describedwith reference to FIG. 9C, the second impurity regions 22 exposed by thecontact holes ECH may be exposed at the substantially same level, as theresult of the selective removal of the second sacrificial patterns 72.

Referring to FIGS. 11A, 11B, and 11C, the contact structures CT may beformed to fill the contact holes ECH. The contact structures CT may beformed by forming a conductive layer to fill the contact holes ECH andperforming an etch-back process. After the formation of the contactstructures CT, the mask pattern 61 may be removed from the peripheralcircuit region PCR. The contact structures CT may include at least oneof a doped polysilicon layer, metals, conductive metal nitride layers,or metal-semiconductor compounds. Due to the presence of the gap regionsGP, the contact structures CT may be formed to have a uniform contactarea with the second impurity regions 22.

Referring back to FIGS. 1A, 1B, and 1C, the second interlayeredinsulating layer 116 may be formed to cover the bit line structures BSand the peripheral gate structure PG, and the contact pads 115 may beconnected to the contact structures CT through the second interlayeredinsulating layer 116. The contact pads 115 may be formed on acorresponding one of the contact structures CT and separated from eachother.

The peripheral contact 186 may be formed to be connected to the thirdimpurity region 23 of the peripheral circuit region PCR. The peripheralcontact 186 may be formed to connect the peripheral conductive line 185provided on the second interlayered insulating layer 116 electrically tothe third impurity region 23. The peripheral conductive line 185 may beelectrically connected to the bit line structures BS, but exampleembodiments of inventive concepts may not be limited thereto.

The third interlayered insulating layer 117 may be formed on the secondinterlayered insulating layer 116, and then, the lower electrodes 182may be formed through the third interlayered insulating layer 117 and beconnected to the contact pads 115. In example embodiments, each of thelower electrodes 182 may be shaped like a bottom-closed cylinder. Theformation of the lower electrodes 182 may include forming a sacrificiallayer (not shown) to expose the contact pads 115, conformally forming aconductive layer on the sacrificial layer, and then, forming agap-filling layer on the conductive layer. Thereafter, an etchingprocess may be performed to the conductive layer to form the lowerelectrodes 182, each of which is connected to a corresponding one of thecontact pads 115, and then, the sacrificial layer and the gap-fillinglayer may be removed.

The contact pads 115 and the lower electrodes 182 may be formed of atleast one of metals, conductive metal compounds or doped semiconductors.The interlayered insulating layers 116 and 117 may be formed of at leastone of silicon oxide, silicon nitride, or silicon oxynitride. Thecontact pads 115, the lower electrodes 182, and the interlayeredinsulating layers 116 and 117 may be formed by a sputtering or CVDprocess.

The dielectric layer 183 and the upper electrode 184 may be sequentiallyformed on the lower electrodes 182. The lower electrodes 182, thedielectric layer 183 and the upper electrode 184 may constitute thecapacitors CAP serving as memory elements of the semiconductor device.The upper electrode 184 may be formed of the substantially same materialas the lower electrodes 182.

In example embodiments, by using the etching process using thesacrificial pattern, it is possible to reduce the variation in depth ofthe contact holes and to maintain or increase a contact area between thecontact structures and the second impurity regions. Accordingly, it ispossible to limit (and/or prevent) a misalignment between the contactstructures and the impurity region or to suppress an increase of leakagecurrent or contact resistance, which may occur by variation in depth ofthe contact structures.

FIGS. 12A through 14A are sectional views taken along the line A-A′ ofFIG. 1A and illustrate semiconductor devices and methods of fabricatingthe same according to example embodiments of inventive concepts. FIGS.12B through 14B are sectional views taken along the lines B-B′ and C-C′of FIG. 1A. For the sake of brevity, the elements and features of thisexample that are similar to those previously shown and described willnot be described in much further detail.

Referring to FIGS. 1A, 12A and 12B, the mask pattern 112 may be removedfrom the resulting structure described with reference to FIGS. 6A, 6B,and 6C, and then, first semiconductor patterns 141 may be formed on thecell array region CAR and the peripheral circuit region PCR. Forexample, the first semiconductor patterns 141 may be formed of a undopedsilicon layer. A mask pattern 113 may be formed on the firstsemiconductor patterns 141, and by using the mask pattern 113 as an etchmask, through holes 18 may be formed to expose the first impurityregions 21 through the first semiconductor patterns 141. In exampleembodiments, the through holes 18 may be formed to have a section shapedlike a circle or an ellipse, in plan view. The through holes 18 may beformed to expose top surface of the first sacrificial patterns 71. Forexample, the formation of the through holes 18 may be performed by anetching process using the first sacrificial patterns 71 as an etch stoplayer.

Referring to FIGS. 1A, 13A, and 13B, the first sacrificial patterns 71exposed by the through holes 18 may be selectively etched or removed.The first impurity regions 21 may be exposed by the removal of the firstsacrificial patterns 71. The selective etching process of the firstsacrificial patterns 71 may be performed using an etching solution or anetching gas, which is selected to suppress the substrate 100 and thedevice isolation layer 101 from being etched and to remove selectivelythe first sacrificial patterns 71. For example, in the case where thefirst sacrificial patterns 71 include silicon-germanium, the selectiveremoval of the first sacrificial patterns 71 may be performed using anetching solution containing peracetic acid. The etching solution mayfurther contain hydrofluoric acid (HF) solution and deionized water. Inexample embodiments, in the case where the first sacrificial pattern 71includes a silicon nitride layer, the selective removal of the firstsacrificial patterns 71 may be performed using an etching solutioncontaining phosphoric acid (H3PO4).

First conductive patterns 148 may be formed on the resulting structure,in which the first sacrificial patterns 71 are removed, to fill thethrough holes 18. Each of the first conductive patterns 148 may includea third portion CP3, which is overlapped with and spaced apart from thedevice isolation layer 101 in plan view, and a fourth portion CP4, whichextends from the third portion CP3 toward the substrate 100 and fill aregion delimited by a top surface of the first impurity region 21 and asidewall of the device isolation layer 101. The fourth portion CP4 maybe shaped like a plug protruding from the third portion CP3 toward thesubstrate 100.

A barrier layer 151, a second conductive layer 161 and a capping layer171 may be sequentially formed on the resulting structure provided withthe first conductive patterns 148. The barrier layer 151 may include atleast one of conductive metal nitrides and/or metal-silicon compounds.The barrier layer 151 may be formed using a CVD or ALD process. Thesecond conductive layer 161 may include at least one of metals,conductive metal nitrides, or metal-silicon compounds. For example, thesecond conductive layer 161 may include at least one of W, Ti, or Ta.The capping layer 171 may include at least one of silicon oxide, siliconnitride or silicon oxynitride. The second conductive layer 161 and thecapping layer 171 may be formed by a sputtering or CVD method.

Referring to FIGS. 1A, 14A, and 14B, bit line structures BS may beformed on the cell array region CAR, and a peripheral gate structure PGmay be formed on the peripheral circuit region PCR. Contact structuresCT may be formed to fill contact holes ECH and be connected to thesecond impurity regions 22, respectively. In example embodiments, thebit line structures BS, the peripheral gate structure PG, and thecontact structures CT may be formed using substantially the same processpreviously described with reference to FIGS. 8A through 11C.

FIGS. 15A through 23A are plan views illustrating methods of fabricatinga semiconductor device according to example embodiments of inventiveconcepts. FIGS. 15B through 23B are sectional views taken along lineA-A′ of FIGS. 15A through 23A, respectively, and FIGS. 15C through 23Care sectional views taken along lines B-B′ and C-C′ of FIGS. 15A through23A, respectively.

Referring to FIGS. 15A, 15B and 15C, the device isolation layers 101 maybe formed on the substrate 100 to delimit the first active regions ACT1in the cell array region CAR and the second active region ACT2 in theperipheral circuit region PCR. The first active regions ACT1 may behorizontally separated from each other to have a bar-shaped structureand extend along a third direction (hereinafter, s direction) at anangle to both of the first direction (hereinafter, x direction) and thesecond direction (hereinafter, y direction). Here, the x direction andthe y direction may be directions crossing each other.

A mask pattern 62 may be formed to cover the peripheral circuit regionPCR, and then, upper portions of the first active regions ACT1 exposedby the device isolation layer 101 may be etched to form recess regionsRS. In example embodiments, the mask pattern 62 may include a siliconoxide layer or a silicon nitride layer. The recess regions RS may bedelimited by the sidewall of the device isolation layer 101 and the topsurface of the substrate 100. The formation of the recess regions RS mayinclude a dry and/or wet etching process.

After the formation of the recess regions RS, impurity regions 20 may beformed in the upper portions of the first active regions ACT1. Theimpurity region 20 may be formed by an ion implantation processinjecting impurities ions with a different conductivity type from thesubstrate 100 into the upper portions of the substrate 100. In otherembodiments, the impurity region 20 may be formed before the formationof the device isolation layer 101 or between the formation of the deviceisolation layer 101 and the formation of the recess regions RS.

Referring to FIGS. 16A, 16B, and 16C, a first etch stop layer 191 and asacrificial layer 75 may be sequentially formed on the resultingstructure provided with the recess regions RS. The sacrificial layer 75may be formed of a material having an etch selectivity with respect tothe substrate 100 and the device isolation layer 101. For example, thesacrificial layer 75 may be formed of at least one of silicon-germaniumcompounds, a silicon nitride layer, a silicon oxynitride layer, orsilicon-metal compounds. The first etch stop layer 191 may include atleast one material that is selected from a group consisting of a siliconnitride layer, a silicon oxynitride layer, metals, metal-siliconcompounds, and conductive metal nitrides but is different from amaterial for the sacrificial layer 75.

Referring to FIGS. 17A, 17B, and 17C, a planarization process may beperformed to confine or localize the first etch stop layer 191 and thesacrificial layer 75 into the recess regions RS. Accordingly, a firstetch stop pattern ST1 and a preliminary sacrificial pattern 78 may belocally formed in each of the recess regions RS. During theplanarization process, the mask pattern 62 may be removed from theperipheral circuit region PCR.

A mask pattern 63 may be formed to cover the peripheral circuit regionPCR, and then, a second etch stop pattern ST2 may be formed on thesubstrate 100. The second etch stop pattern ST2 may include at least onematerial that is selected from a group consisting of a silicon nitridelayer, a silicon oxynitride layer, metals, metal-silicon compounds, andconductive metal nitrides but is different from a material for thesacrificial layer 75.

Referring to FIGS. 18A, 18B and 18C, trenches 11 may be formed to extendtoward the top surface of the substrate 100 through the second etch stoppattern ST2 of the cell array region CAR. The trenches 11 may be formedby an etching process using a mask pattern 111 as an etch mask. Thetrenches 11 may extend along the y direction and be spaced apart fromeach other in the x direction, such that the impurity region 20 may beseparated into the first impurity regions 21 and the second impurityregions 22. In other words, in each of the first active region ACT1, thefirst impurity region 21 may be provided between a pair of the secondimpurity regions 22, and the first impurity region 21 and the secondimpurity regions 22 may be separated from each other by the trenches 11.The trenches 11 may separate the preliminary sacrificial pattern 78 intoa plurality of sacrificial patterns. The sacrificial patterns mayinclude first sacrificial patterns 76 on the first impurity regions 21and second sacrificial patterns 77 on the second impurity regions 22.

A first insulating layer 120, a conductive layer 125, and a fillinglayer 128 may be sequentially formed on the resulting structure providedwith the trenches 11. The first insulating layer 120 and the conductivelayer 125 may be formed in the trenches 11, and then, the filling layer128 may be formed to fill the trenches 11 provided with the firstinsulating layer 120 and the conductive layer 125. The formation of thefilling layer 128 may include forming an insulating layer on theconductive layer 125 and then performing a planarization process.

Referring to FIGS. 19A, 19B, and 19C, the first insulating layer 120 andthe conductive layer 125 may be etched and localized into the trenches11. As the result of the etching process, the first insulating layer 120may form the gate insulating layers 121 separated from each other andthe conductive layer 125 may form the gate electrodes 126 separated fromeach other. The etching process may be performed until the filling layer128 is removed, and thus, the gate insulating layers 121 and the gateelectrodes 126 may have top surfaces that are lower than top surfaces ofthe trenches 11. The mask pattern 111 may be removed during the etchingprocess. The first insulating layer 120 and the conductive layer 125provided on the peripheral circuit region PCR may be removed during theetching process.

The gate capping patterns 129 may be formed on the gate electrodes 126.The gate capping patterns 129 may be formed by forming an insulatinglayer to fill remaining portions of the trenches 11 provided with thegate electrodes 126 and performing a planarization process to expose thetop surface of the substrate 100. The insulating layer provided on theperipheral circuit region PCR may be removed by the planarizationprocess. The gate capping patterns 129 may include at least one of asilicon nitride layer, a silicon oxide layer, or a silicon oxynitridelayer. As the result of the formation of the gate capping patterns 129,cell gate structures may be formed in the trenches 11. The cell gatestructures may serve as word line structures WS of the semiconductordevice.

A second insulating layer 131 may be formed on the peripheral circuitregion PCR. The second insulating layer 131 may include at least one ofsilicon oxide, silicon oxynitride, or high-k dielectrics having a higherdielectric constant than silicon oxide.

The first semiconductor patterns 141 may be formed on the cell arrayregion CAR and the peripheral circuit region PCR. For example, the firstsemiconductor patterns 141 may be formed of an un-doped silicon layer.Through holes 12 may be formed to expose the first impurity regions 21through the first semiconductor patterns 141. The first sacrificialpatterns 76 may be removed by the formation of the through holes 12. Inexample embodiments, the through holes 12 may be formed to have asection shaped like a circle or an ellipse, in plan view. The formationof the through holes 12 may include forming a mask pattern 113 on thefirst semiconductor patterns 141, and then, performing a dry and/or wetetching process using the mask pattern 113 as an etch mask. The firstsemiconductor patterns 141 on the peripheral circuit region PCR may bedoped with impurities ions, before or after the formation of the throughholes 12. In example embodiments, a mask pattern (not shown) may beformed to cover the cell array region CAR, and an ion implantationprocess may be performed to the first semiconductor patterns 141 on theperipheral circuit region PCR. The first semiconductor patterns 141doped with impurities may have a conductivity type of p- or n-type,depending on whether the transistor on the peripheral circuit region PCRis a PMOS transistor or an NMOS transistor.

Referring to FIGS. 20A, 20B, and 20C, the first conductive patterns 147may be formed to fill the through holes 12. In example embodiments, thefirst conductive patterns 147 may be a doped silicon layer. The firstconductive patterns 147 may be formed by removing the mask pattern 113,forming a semiconductor layer to fill the through holes 12, and then,performing a planarization process. The first conductive patterns 147may be doped in an in-situ manner and have the same conductivity type asthe first impurity regions 21.

A barrier layer, a second conductive layer and a capping layer may besequentially formed on the resulting structure provided with the firstconductive patterns 147. The first semiconductor patterns 141, thebarrier layer, the second conductive layer and the capping layer may bepatterned to form conductive lines on the cell array region CAR and aperipheral gate structure PG on the peripheral circuit region PCR. Theconductive lines may serve as bit line structures BS of thesemiconductor device. The bit line structures BS may include a pluralityof first conductive patterns 147 coupled to the first impurity regions21, respectively, and the barrier pattern 152, the second conductivepattern 162, and the capping pattern 172 sequentially stacked on thefirst conductive patterns 147. The peripheral gate structure PG mayinclude the gate insulating layer 132, the first conductive pattern 143,the barrier pattern 153, the second conductive pattern 163 and thecapping pattern 173 that are sequentially stacked on the substrate 100.The formation of the bit line structures BS and the peripheral gatestructure PG may include forming first spacers SP1 and second spacersSP2 on sidewalls of the bit line structures BS and the peripheral gatestructure PG, respectively.

The third impurity region 23 may be formed in the substrate 100 of theperipheral circuit region PCR to be adjacent to the peripheral gatestructure PG. The formation of the third impurity region 23 may includean ion implantation process to be performed on the substrate 100 exposedby the peripheral gate structure PG, and the ion implantation processmay be performed using impurities having the same conductivity type asthe first conductive pattern 143.

The first interlayered insulating layer 81 may be formed on theresulting structure provided with the bit line structures BS and theperipheral gate structure PG. The first interlayered insulating layer 81may be formed to fill empty spaces between the bit line structures BS.For example, the first interlayered insulating layer 81 may include asilicon oxide layer and/or a silicon oxynitride. As the result of theplanarization process, the first interlayered insulating layer 81 may beformed to expose top surfaces of the capping patterns 172 and 173. Amask pattern 61 may be formed on the first interlayered insulating layer81. In the cell array region CAR, the mask pattern 61 may be formed tocross the bit line structures BS. In example embodiments, the maskpattern 61 may be formed to have a line shape extending parallel to theword line structures WS. The peripheral circuit region PCR may becovered with the mask pattern 61.

Referring to FIGS. 21A, 21B, and 21C, the first interlayered insulatinglayer 81 exposed by the mask pattern 61 may be etched to formpreliminary contact holes CH. The formation of the preliminary contactholes CH may include an etching process, in which the second etch stoppattern ST2 is used. As the result of the etching process, the secondsacrificial patterns 77 may be exposed. During the etching process, thebit line structures BS exposed by the mask pattern 61 may be protectedby the capping pattern 172 and the first spacer SP1. As the result ofthe etching process, the first interlayered insulating layer 81 on thecell array region CAR may be separated into the first interlayeredinsulating patterns 82 spaced apart from each other. Alternatively, thefirst interlayered insulating layer 81 on the peripheral circuit regionPCR may be protected by the mask pattern 61. The preliminary contactholes CH may be delimited by sidewalls of the bit line structures BS andsidewalls of the first interlayered insulating patterns 82.

Referring to FIGS. 22A, 22B, and 22C, the second sacrificial patterns 72exposed by the preliminary contact holes CH may be removed to form thegap regions GP exposing the second impurity regions 22. The gap regionsGP may be delimited by the sidewall of the device isolation layer 101and the top surfaces of the second impurity regions 22. As the result ofthe formation of the gap regions GP, the preliminary contact holes CHmay extend toward the substrate 100 and form the contact holes ECH. Theremoval of the second sacrificial patterns 77 may include a selectiveetching process. The first etch stop pattern ST1 may limit (and/orprevent) the second impurity regions 22 from being damaged by etchingsolution or etching gas to be used in the removal of the secondsacrificial patterns 77. Thereafter, the first etch stop pattern ST1 maybe removed to expose the second impurity regions 22.

Referring to FIGS. 23A, 23B, and 23C, the contact structures CT may beformed to fill the contact holes ECH. The contact structures CT may beformed by forming a conductive layer to fill the contact holes ECH andperforming an etch-back process. After the formation of the contactstructures CT, the mask pattern 61 may be removed from the peripheralcircuit region PCR. The contact structures CT may include at least oneof a doped polysilicon layer, metals, conductive metal nitride layers,or metal-semiconductor compounds. Due to the presence of the gap regionsGP, the contact structures CT may be formed to have a uniform contactarea with the second impurity regions 22.

FIGS. 24A and 24B are sectional views illustrating semiconductor devicesaccording to example embodiments of inventive concepts. Here, FIG. 24Ais a sectional view taken along line A-A′ of FIG. 23A, and FIG. 24B is asectional view taken along lines B-B′ and C-C′ of FIG. 23A. For the sakeof brevity, the elements and features of this example that are similarto those previously shown and described will not be described in muchfurther detail.

In example embodiments, the removal of the first etch stop pattern ST1described with reference to FIGS. 22A, 22B, and 22C may be omitted, andthe first etch stop pattern ST1 may remain between the contactstructures CT and the second impurity regions 22. For example, the firstetch stop pattern ST1 may include at least one of metals, conductivemetal nitrides, or metal-silicon compounds.

FIGS. 25A through 29A are plan views illustrating methods of fabricatinga semiconductor device according to example embodiments of inventiveconcepts, FIGS. 25B through 29B are sectional views taken along lineA-A′ of FIGS. 25A through 29A, respectively, and FIGS. 25C through 29Care sectional views taken along lines B-B′ and C-C′ of FIGS. 25A through29A, respectively.

Referring to FIGS. 25A, 25B, and 25C, first interlayered insulatingpatterns 83 may be formed between the bit line structures BS. Theformation of the first interlayered insulating patterns 83 may includeforming a first interlayered insulating layer 81 to cover the bit linestructures BS and the peripheral gate structure PG described withreference to FIGS. 8A, 8B, and 8C, and then, etching the firstinterlayered insulating layer 81 using mask patterns 67, which may beformed parallel to the word line structures WS, as an etch mask. Themask patterns 67 may cover the peripheral gate structure PG, and thefirst interlayered insulating layer 81 may remain on the peripheralcircuit region PCR. Hole regions HR may be formed by the etchingprocess. The hole regions HR may be delimited by sidewalls of the bitline structures BS and a sidewall of the first interlayered insulatingpattern 83. At least some of the hole regions HR may be formed to have adifferent depth from others of the hole regions HR. For example, adistance from the top surfaces of the gate capping patterns 129 to thetop surfaces of the second sacrificial patterns 72 exposed by the holeregions HR may have several different values (e.g., d4, d5, and d6,where d4>d6>d5), as shown in FIG. 25C.

Referring to FIGS. 26A, 26B, and 26C, gap-filling patterns 87 may beformed to extend between the mask patterns 67 and fill the hole regionsHR. The gap-filling patterns 87 may be formed of a material having anetch selectivity with respect to the first interlayered insulatingpatterns 83. For example, in the case where the first interlayeredinsulating patterns 83 include a silicon oxide layer, the gap-fillingpatterns 87 may include a silicon nitride or a silicon oxynitride. Theformation of the gap-filling patterns 87 may include forming aninsulating layer to fill the hole regions HR, and performing aplanarization process to expose the mask patterns 67.

Referring to FIGS. 27A, 27B, and 27C, a mask pattern 68 may be formed onthe peripheral circuit region PCR, and then, the first interlayeredinsulating patterns 83 may be selectively removed from the cell arrayregion CAR. As the result of the removal of the first interlayeredinsulating patterns 83, preliminary contact holes CH may be formed toexpose the second sacrificial patterns 72.

Referring to FIGS. 28A, 28B, and 28C, the second sacrificial patterns 72exposed by the preliminary contact holes CH may be removed to form thegap regions GP exposing the second impurity regions 22. The gap regionsGP may be delimited by the sidewall of the device isolation layer 101and the top surfaces of the second impurity regions 22. As the result ofthe formation of the gap regions GP, the preliminary contact holes CHmay extend toward the substrate 100 and form the contact holes ECH. Theremoval of the second sacrificial patterns 72 may include a selectiveetching process. For example, the selective etching process of thesecond sacrificial patterns 72 may be performed using an etchingsolution or an etching gas capable of suppressing the substrate 100 andthe device isolation layer 101 from being etched and of selectivelyremoving the second sacrificial patterns 72. For example, in the casewhere the second sacrificial patterns 72 include silicon-germanium, theselective removal of the second sacrificial patterns 72 may be performedusing an etching solution containing peracetic acid. The etchingsolution may further contain hydrofluoric acid (HF) solution anddeionized water. In example embodiments, in the case where the secondsacrificial patterns 72 include a silicon nitride layer, the selectiveremoval of the second sacrificial patterns 72 may be performed using anetching solution containing phosphoric acid (H₃PO₄).

Referring to FIGS. 29A, 29B, and 29C, the contact structures CT may beformed to fill the contact holes ECH. The contact structures CT may beformed by forming a conductive layer to fill the contact holes ECH andperforming an etch-back process. After the formation of the contactstructures CT, the mask patterns 67 and 68 may be removed from theperipheral circuit region PCR. The contact structures CT may include atleast one of a doped polysilicon layer, metals, conductive metal nitridelayers, or metal-semiconductor compounds. Due to the presence of the gapregions GP, the contact structures CT may be formed to have a uniformcontact area with the second impurity regions 22.

The second interlayered insulating layer 116 may be formed to cover thebit line structures BS and the peripheral gate structure PG, and thecontact pads 115 may be connected to the contact structures CT throughthe second interlayered insulating layer 116. The contact pads 115 maybe formed on a corresponding one of the contact structures CT and beseparated from each other.

The peripheral contact 186 may be formed to be connected to a thirdimpurity region 23 of the peripheral circuit region PCR. The peripheralcontact 186 may be formed to connect the peripheral conductive line 185provided on the second interlayered insulating layer 116 electrically tothe third impurity region 23. The peripheral conductive line 185 may beelectrically connected to the bit line structures BS, but exampleembodiments of inventive concepts may not be limited thereto.

The third interlayered insulating layer 117 may be formed on the secondinterlayered insulating layer 116, and then, the lower electrodes 182may be formed through the third interlayered insulating layer 117 and beconnected to the contact pads 115. In example embodiments, each of thelower electrodes 182 may be shaped like a bottom-closed cylinder. Thedielectric layer 183 and the upper electrode 184 may be sequentiallyformed on the lower electrodes 182. The lower electrodes 182, thedielectric layer 183 and the upper electrode 184 may constitute thecapacitors CAP serving as memory elements of the semiconductor device.

The semiconductor memory devices disclosed above may be encapsulatedusing various and diverse packaging techniques. For example, thesemiconductor memory devices according to the aforementioned embodimentsmay be encapsulated using any one of a package on package (POP)technique, a ball grid arrays (BGAs) technique, a chip scale packages(CSPs) technique, a plastic leaded chip carrier (PLCC) technique, aplastic dual in-line package (PDIP) technique, a die in waffle packtechnique, a die in wafer form technique, a chip on board (COB)technique, a ceramic dual in-line package (CERDIP) technique, a plasticquad flat package (PQFP) technique, a thin quad flat package (TQFP)technique, a small outline package (SOIC) technique, a shrink smalloutline package (SSOP) technique, a thin small outline package (TSOP)technique, a system in package (SIP) technique, a multi-chip package(MCP) technique, a wafer-level fabricated package (WFP) technique and awafer-level processed stack package (WSP) technique. The package inwhich the semiconductor memory device according to example embodimentsis mounted may further include at least one semiconductor device (e.g.,a controller and/or a logic device) that controls the semiconductormemory device.

FIG. 30 is a block diagram schematically illustrating electronic devicesincluding a semiconductor device according to example embodiments ofinventive concepts.

Referring to FIG. 30, an electronic device 1300 including asemiconductor device according to example embodiments of inventiveconcept may be used in one of a personal digital assistant (PDA), alaptop computer, a mobile computer, a web tablet, a wireless phone, acell phone, a digital music player, a wire or wireless electronicdevice, or a complex electronic device including at least two onesthereof. The electronic device 1300 may include a controller 1310, aninput/output device 1320 such as a keypad, a keyboard, a display, amemory 1330, and a wireless interface 1340 that are combined to eachother through a bus 1350. The controller 1310 may include, for example,at least one microprocessor, a digital signal process, a microcontrolleror the like. The memory 1330 may be configured to store a command codeto be used by the controller 1310 or a user data. The memory 1330 mayinclude a semiconductor device including a vertical channel transistoraccording to example embodiments of inventive concept. The electronicdevice 1300 may use a wireless interface 1340 configured to transmitdata to or receive data from a wireless communication network using a RFsignal. The wireless interface 1340 may include, for example, anantenna, a wireless transceiver and so on. The electronic system 1300may be used in a communication interface protocol of a communicationsystem such as CDMA, GSM, NADC, E-TDMA, WCDMA, CDMA2000, Wi-Fi, MuniWi-Fi, Bluetooth, DECT, Wireless USB, Flash-OFDM, IEEE 802.20, GPRS,iBurst, WiBro, WiMAX, WiMAX-Advanced, UMTS-TDD, HSPA, EVDO,LTE-Advanced, MMDS, and so forth.

FIG. 31 is a block diagram schematically illustrating memory systemsincluding a semiconductor device according to example embodiments ofinventive concepts.

Referring to FIG. 31, a memory system including a semiconductor deviceaccording to example embodiments of inventive concept will be described.The memory system 1400 may include a memory device 1410 for storing hugeamounts of data and a memory controller 1420. The memory controller 1420controls the memory device 1410 so as to read data stored in the memorydevice 1410 or to write data into the memory device 1410 in response toa read/write request of a host 1430. The memory controller 1420 mayinclude an address mapping table for mapping an address provided fromthe host 1430 (e.g., a mobile device or a computer system) into aphysical address of the memory device 1410. The memory device 1410 maybe a semiconductor device including a vertical channel transistoraccording to example embodiments of inventive concepts.

According to example embodiments of inventive concepts, it is possibleto realize a semiconductor device with improved electriccharacteristics.

While some example embodiments of inventive concepts have beenparticularly shown and described, it will be understood by one ofordinary skill in the art that variations in form and detail may be madetherein without departing from the spirit and scope of the attachedclaims.

1. A semiconductor device, comprising: a substrate having an uppersurface, the upper surface of the substrate defining a groove and anactive region; a device isolation layer in the groove of the substrate,the device isolation layer exposing the active region and having a topsurface that is higher than a top surface of the active region of thesubstrate; and a contact structure on the active region of thesubstrate, the contact structure including a first portion that fills agap region delimited by a sidewall of the device isolation layer and thetop surface of the active region, and the contact structure including asecond portion on the device isolation layer so the second portionoverlaps the device isolation layer in a plan view.
 2. The device ofclaim 1, wherein the first portion contacts the sidewall of the deviceisolation layer, and the first portion contacts the top surface of theactive region.
 3. The device of claim 2, wherein the active regionincludes a first active region in a cell array region of the substrate,the first active region includes a first impurity region and a secondimpurity region, and a bottom surface of the first portion covers anentire area of a top surface of the second impurity region in the firstactive region.
 4. The device of claim 1, further comprising: conductivelines on the substrate, wherein the second portion is between theconductive lines, and the first portion extends below the conductivelines.
 5. The device of claim 1, further comprising: a cell gatestructure buried in the substrate, wherein a portion of the gap regionis delimited by a sidewall of the cell gate structure.
 6. The device ofclaim 5, wherein a sidewall of the first portion is in contact with thesidewall of the cell gate structure.
 7. The device of claim 5, whereinthe active region comprises a first impurity region and a secondimpurity region, the first impurity region and the second impurityregion are at both sides of the cell gate structure, and the contactstructure is connected to the second impurity region.
 8. The device ofclaim 7, further comprising: a data storing element connected to thecontact structure.
 9. The device of claim 8, wherein the data storingelement comprises a lower electrode, an upper electrode and aninsulating layer, and the insulating layer is between the lower andupper electrodes.
 10. The device of claim 7, further comprising:conductive lines on the substrate, wherein the conductive lines crossthe cell gate structure, and the first impurity region is connected tothe conductive lines.
 11. The device of claim 10, wherein each of theconductive lines comprises a third portion and a fourth portion, thethird portion overlaps with the device isolation layer in a plan view,the fourth portion extends from the third portion toward the substrate,and the fourth portion fills a region delimited by the sidewall of thedevice isolation layer and a top surface of the first impurity region.12. The device of claim 10, further comprising: a first interlayeredinsulating pattern between the conductive lines, the first interlayeredinsulating pattern delimiting the second portion along with theconductive lines; and an etch stop layer between the device isolationlayer and the conductive lines, the etch stop layer including a materialhaving an etch selectivity with respect to the first interlayeredinsulating pattern.
 13. The device of claim 5, wherein the top surfaceof the device isolation layer defines a trench, and the cell gatestructure comprises, a gate insulating layer in the trench, a gateconductive layer in the trench and on the gate insulating layer, and acapping layer on top surfaces of the gate insulating layer and the gateconductive layer, the capping layer filling the trench.
 14. The deviceof claim 13, further comprising: a peripheral gate structure, whereinthe upper surface of the substrate includes a cell region and aperipheral circuit region, the cell gate structure is on the cell regionof the substrate, the peripheral gate structure is on the peripheralcircuit region of the substrate, and the upper surface of the substratein the peripheral circuit region is lower than an upper surface of thecapping layer.
 15. The device of claim 1, wherein the contact structurefurther comprises a conductive etch stop layer between the first portionand the active region, and the conductive etch stop layer extends alongthe sidewall of the device isolation layer.
 16. A semiconductor device,comprising: a substrate; a device isolation layer on the substrate, thedevice isolation layer exposing an active region of a substrate;conductive lines on the substrate; and a contact structure providedbetween the conductive lines, the contact structure connected to theactive region, and the contact structure including a lower portion thatextends below the conductive lines.
 17. The device of claim 16, whereinthe lower portion of the contact structure fills a gap region delimitedby a sidewall of the device isolation layer and a top surface of theactive region.
 18. The device of claim 16, wherein the contact structurecomprises an upper portion, and the upper portion overlaps with thedevice isolation layer in a plan view.
 19. The device of claim 16,further comprising: a cell gate structure buried in the substrate,wherein a portion of the gap region is delimited by a sidewall of thecell gate structure.
 20. The device of claim 19, wherein the activeregion of the substrate includes a first impurity region and a secondimpurity region, the first impurity region and the second impurityregion are at both sides of the cell gate structure, the contactstructure is connected to the second impurity region, and each of theconductive lines are connected to the first impurity region. 21.-40.(canceled)
 41. A semiconductor device, comprising: a substrate having anupper surface, the upper surface of the substrate defining first activeregions that protrude from the substrate and are separated by a groove,each one of the first active regions including a first impurity regionbetween a pair of second impurity regions; and a plurality of contactstructures that are spaced apart from each other, the plurality ofcontact structures each including a first portion on a corresponding oneof the second impurity regions and a second portion that extendsvertically from a part of an upper surface of the first portion, eachsecond portion including a lower surface that partially overlaps thegroove in a plan view.
 42. The semiconductor device of claim 41, furthercomprising: a device isolation layer in the groove, wherein the deviceisolation layer exposes the first active regions, the device isolationincludes a top surface that is higher than a top surface of the firstactive regions.
 43. The semiconductor device of claim 42, furthercomprising: a plurality of bit lines that are spaced apart from eachother on the substrate, wherein the bit lines extend in a firstdirection, and each one of the bit lines is electrically connected tothe first impurity region and electrically isolated from the secondimpurity regions of at least two adjacent first active regions.
 44. Thesemiconductor device of claim 43, further comprising: a plurality ofword line structures embedded in the device isolation layer, wherein theplurality of word line structures extend in a second direction crossingthe first direction.
 45. The semiconductor device of claim 41, furthercomprising: a peripheral gate structure, wherein the substrate includesa cell array region and a peripheral circuit region, the first activeregions are in the cell array region of the substrate, the upper surfaceof the substrate further defines a second active region in theperipheral circuit region of the substrate, the second active region isspaced apart from the first active regions, and the peripheral gatestructure is on the second active region.